The present invention relates generally to integrated circuit delay characterization; and, more particularly, it relates to delay characterization that is attributable to electrical interference due to cross coupling capacitance within integrated circuits.
Conventional methods that are used to perform delay characterization of integrated circuits fail to provide accurate measurement and subsequently inhibit the ability of designers to integrate properly various integrated circuits within a system. In addition, the inability to provide accurate delay characterization of integrated circuits provides an undesirability, in that, manufacturers are incapable of giving detailed specification for their integrated circuits within a high degree of accuracy.
The difficulty in estimating the worst case delay in the presence of noise within an integrated circuit is complicated by the intrinsic non-linearities of the gates driving the nets within an integrated circuit. This intrinsic non-linearity within the system necessitates significant processing resources using conventional non-linear circuit analysis tools such a Spice, P-Spice, etc. This processing is further complicated, in that, the total number of linear elements of the entire integrated circuit is typically very large. Within integrated circuits that have undesirable parasitic cross-coupling, the alignment of the transition times between victim and aggressor devices is additionally very difficult. Another difficulty is that the alignment of what is thought to be a worst-case delay at a receiver input within the integrated circuit does not always yield the worst case delay at the same receiver output within the integrated circuit. Many conventional methods to perform delay characterization focus on characterization at the receiver input.
Conventional methods that attempt to model the delay of integrated circuits generally fail to provide the degree of accuracy that is desired within the industry. One conventional method involves grounding the coupling capacitors between devices within the integrated circuit. However, this conventional method typically underestimates the worst case delay of the integrated circuit. Another conventional method involves increasing the value of grounded capacitors by a predetermined value, i.e., by a factor of two (2xc3x97). However, this conventional method is typically not very conservative, in that, the increase of the real value of the grounded capacitors could be as high as a factor of five (5xc3x97). In addition, this conventional method may overestimate the delay on some nets thereby yielding a sub-optimal design. Another conventional method involves manual manipulation of the known critical nets within an integrated circuit using conventional circuit analysis tools such a Spice, P-Spice, etc. The problems with this conventional method are many, in that, the simulation time required to perform these manual manipulations can be extremely large. In addition, the manual intervention of this conventional method may result in missing what were thought to be non-critical nets when they do in fact become critical nets due to the noise. Furthermore, the inherent manual intervention of this conventional method requires an exhaustive search to find the worst case delay within the integrated circuit.
Another conventional method uses the alignment of noise to obtain a 50% delay at the victim receiver input. This conventional method is easy to be done using superposition. However, as briefly described above, those conventional methods that look only to the victim receiver inputs inherently ignore the effect of the victim receiver and therefore can result in improper delay alignment. Also, to minimize the complexity of the analysis performed with this conventional method, the method uses a standard Thevenin linear gate model for the victim driver which tends to underestimate delay changes. The use of the standard Thevenin linear gate model for the victim driver is simply an inaccurate representation of the victim driver. The conventional methods described above that perform delay characterization simply do not provide for a highly accurate, computationally efficient way to perform the delay characterization of integrated circuits.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.